A clock-tuning circuit for system-on-chip
نویسندگان
چکیده
منابع مشابه
A clock-tuning circuit for system-on-chip
In SoC design, multiple buffered clock distribution networks are typically used to drive the large clock loads of the different clock domains. Chip design involves a clock alignment step, which equalizes the delay from the clock source to each and every flop. Accurate clock alignment is important, because unwanted differences or uncertainties in clock network delays may degrade performance or c...
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ژورنال
عنوان ژورنال: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
سال: 2003
ISSN: 1063-8210,1557-9999
DOI: 10.1109/tvlsi.2003.812371